A split-gate cell is a type of flash or non-volatile memory (NVM) cell, in which a select gate is placed adjacent a memory gate, providing lower current during hot-carrier-based programming operation. During the programming of the split-gate cell, the select gate is biased at a relatively low voltage, and only the memory gate is biased at the high voltage to provide the vertical electric field necessary for hot-carrier injection. Since the acceleration of the carriers takes place in the channel region mostly under the select gate, the relatively low voltage on the select gate above that region results in more efficient carrier acceleration in the horizontal direction compared to the conventional memory cell. That makes the hot-carrier injection more efficient with lower current and lower power consumption during the programming operation. A split-gate cell may be programmed using techniques other than hot-carrier injection, and depending on the technique, any advantage over the conventional NVM memory cell during the programming operation may vary.
Fast read time is another advantage of the split-gate cell. Because the select gate is in series with the memory gate, the erased state of the memory gate can be near or in depletion mode (i.e., threshold voltage, Vt, less than zero volt). Even when the erased memory gate is in such depletion mode, the select gate in the off state prevents the channel from conducting substantial current. With the threshold voltage of the erase state at or below zero, the threshold voltage of the programmed state does not need to be very high while still providing a reasonable read margin between the erased and the programmed states. The resulting voltages applied to both the select gate and the memory gate in read operation are less than or equal to the supply voltage. Therefore, not having to pump the supply voltage to a higher level makes the read operation faster.
It is becoming increasingly common to monolithically incorporate multiple logic devices or transistors on the same substrate as the memory cells to provide improved efficiency, security, functionality, and reliability. However, incorporating logic devices on the same substrate along with the split-gate cell is challenging as each requires different fabrication parameters.
For example, one type of logic device that it is desirable to include with a semiconductor device having an embedded NVM memory employs metal-gate logic transistors for the logic devices. According to some methods, the metal-gate logic transistors are made using gate replacement process including one or more chemical mechanical polishing (CMP) steps in which an interlevel dielectric is planarized to expose a sacrificial gate that is then replaced by a metal-gate that is again planarized using a CMP process. However, due to gate height restrictions for the latest generation of metal-gate logic transistors at geometries of 28 nanometers and beyond, it is not possible to integrally form a flash memory cell on a single substrate with the logic transistors, since the taller gates of the flash memory cell devices would be damaged during the CMP process involved in forming the metal-gate.
Accordingly, there is a need for a semiconductor device integrating split-gate flash cells and metal-gate logic transistors on the same substrate and methods for making such a semiconductor device with improved performance, cost, and manufacturability.